ISA bus (Industry Standard Architecture) Signal Description and
Industry Standard Architecture (ISA) Signal Descriptions
- SA0 to SA19
System Address bits 0 to 19 are used to address memory and I/O devices.
Only the lower 16 bits are used during I/O operations to address up to 64K I/O
SA0 is the least significant bit.
SA19 is the most significant bit.
These signals are gated on the system bus when BALE is high and are latched on the falling edge of BALE. They remain valid throughout a read or write command. These signals are normally driven by the system microprocessor or DMA controller, but may also be driven by a bus master on an ISA board that takes ownership of the bus.
- BALE: Bus Address Latch Enable (also sometimes abbreviated
to ALE = Address Latch Enable).
The address bus is latched on the rising
edge of this signal. The address on the bus is valid from the
falling edge of BALE to the end of the bus cycle.
Address Enable is used to degate the system microprocessor and
other devices from the bus during DMA transfers. When this signal is
active the system DMA controller has control of the address, data, and
read/write signals. This signal should be included as part of ISA board
select decodes to prevent incorrect board selects during DMA cycles.
- SD0 to SD15
System Data serves as the data bus bits for devices on the ISA bus.
SD15 is the most significant bit. SD0 is the least significant bits.
SD0 to SD7 are used for transfer of data with 8-bit devices (e.g. this
lab). SD0 to SD15 are used for transfer of data with 16-bit devices.
I/O Read is driven by the owner of the bus and instructs the selected I/O device to drive read data onto the data bus.
I/O Write is driven by the owner of the bus and instructs the selected I/O device to capture the write data on the data bus.
ISA Bus Timing Diagrams
8-Bit I/O Bus Cycles
AEN __| |_________________________________________
_ ______________________________________________ __