lab9: a good possibility is circuit to drive 2 vga...
PIPELINING continued
brief historical notes on pipelining
fully pipelined means we can start one instruction while finishing another
pipelining hazards:
- data hazards (solved by forwarding)
- control hazards (loops, branches, etc.) solved by determining whether or
not the branch is taken and the target, earlier in the pipeline
(e.g. test for BEQ or BNE opcodes by the end of the instruction decode
register setup cycle: zero test hardware with additional adder inside
the instruction decoder rather than waiting until the ALU stage
of the pipeline).
- structural hazards (same part of microprocessor, e.g. registers, accessed)
accessing same parts of silicon: resource conflicts.
solved by such methods as using separate instruction cache (for FETCH)
and separate data cache for MEM.
structural hazard would
for example result from memory access of
instruction fetch and memory access of data, were it not for
separate data and instruction caches.
existence of cache makes the instruction fetch
(from memory) and the data memory access (also from memory) as fast as
other elements along the pipeline, and solves some of the other problems
also, the register "file" is dual ported so it can read 2 registers at once.
control hazards
flushing of the pipeline if the branch is taken:
FETCH DECODE ALU EXE MEMORY WRITE
FETCH idle idle idle idle
desire to know if taken as early as possible (as described above),
or we can also delay the branch.
forwarding: for example, results of register write can be forwarded directly to
the ALU.
beyond the traditional 5 stage pipeline
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