architectural details of pipelining

decode+memory access Structural Hazard solved by cache.


A structural hazard would for example result from memory access of instruction fetch and memory access of data, were it not for separate data and instruction caches:

another example of a structural hazard is when decoding (setting up input registers) makes reference to same register as a register write:

brief note on cache

note, of course, that the existence of cache makes the instruction fetch (from memory) and the data memory access (also from memory) as fast as other elements along the pipeline.

delay between setup and use of registers:

ram delay versus register delay.

but register access is at L1 cache speed.

L1 operates at same speed as the CPU core, registers, etc..

allows pipeline to do one cycle memory access.

cache levels:

  1. L1 cache: inside the die itself.
    runs at processor speed (e.g. 100MHz, 500MHz, 600MHz, or the like).
  2. L2 cache: speed of external...
    DEC alpha: 83MHz instead of 600MHz of level 1 cache.
    L2 cache is comprised of external ICs.
  3. RAM: 100MHz SD RAM can't go at 100MHz (that's the bus speed); may take several bus cycles to access.
  4. hard drive: note that instructions originate from hard drive, are "cached" in RAM, and then RAM is further cached in cache.
  5. backup tape: archives, etc..
microprocessor rationale: speed of light fixed, so speedup by moving components closer together.

example: inclusion of L1 cache on same die for speedup: line drivers dissipate power; capacitance of copper wire from die to leads...

architectural details of pipelining